`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Wuhan University 
// Engineer: Yu Zihao 
// 
// Create Date: 2021/08/10 12:45:42
// Design Name: 
// Module Name: RAM
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module RAM(clk,read_address,write_address,write,din,dout);
  parameter data_width = 32; 
  parameter addr_width = 4;
  parameter filename = "data.txt";

  input clk;
  input [addr_width-1:0] read_address, write_address;
  input write;
  input [data_width-1:0] din;
  output [data_width-1:0] dout;
  reg [data_width-1:0] dout;

  reg [data_width-1:0] mem [2**addr_width-1:0];

  initial $readmemb(filename, mem);

  always @ (posedge clk) begin
    if (write)
      mem[write_address] <= din;
    dout <= mem[read_address]; // dout doesn't get din in this clock cycle 
                               // (this is due to Verilog non-blocking assignment "<=")
  end 
endmodule

//module ram_tb();
//reg clk;
//reg [8-1:0] read_address, write_address;
//reg write;
//reg [16-1:0] din;
//wire [16-1:0] dout;
//RAM #(.filename("./sas/test.txt"),.addr_width(8),.data_width(16)) ram_tb0 (clk,read_address,write_address,write,din,dout);

//initial begin
//    clk = 0;
//    repeat(500) #5
//    begin
//        clk <= ~clk;
//    end
//    $stop;
//end

//endmodule